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With this open database, you can mine microprocessor trends over the past 40 years.
— This paper describes a parallelized very high radix scalable Montgomery multiplier designed for non-redundant FPGA implementations. It improves on the very high radix scalable architecture by using techniques to parallelize the two multiplications within each processing element. The new design can perform 1024-bit modular exponentiation in 5.0 ms and… (More)
This paper describes a very high radix scalable Montgomery multiplier. It extends the radix-2 Tenca-Kog scalable architecture using w /spl times/ v - bit integer multipliers in place of AND gates. The design can perform 1024-bit modular exponentiation in 6.6 ms using 2847 4-input lookup tables and 32 16 /spl times/ 16 multipliers, making it the fastest… (More)
This study applied specific aspects of signal detection theory (target salience and decision payoffs) to examine the associations among measured attention and accuracy on a stimulus discrimination task patterned after prescription checking. 85 participants completed the d2 Test of Attention and were assigned to either a control condition with general task… (More)
The drive for low-power, high performance computation coupled with the extremely high design costs for ASIC designs, has driven a number of designers to try to create a flexible, universal computing platform that will supersede the microprocessor. We argue that these flexible, general computing chips are trying to accomplish more than is commercially… (More)
We are building a new hand with 18 DOF which has all its actuators inside the body of the hand. This hand is in a form suitable for the 50% women but has the strength capabilities of a 50% male.
Hardware modules would be much easier to reuse if they supported generic flexible high-level interfaces. However, these interfaces are rarely used since they lead to timing and area overheads compared to a customized design. This paper describes a reachability analysis framework that identifies over-provisioning in instances of flexible design, and offers a… (More)
Creating parameterized “chip generators” has been proposed as one way to decrease chip NRE costs. While many approaches are available for creating or generating flexible data path elements, the design of flexible controllers is more problematic. The most common approach is to create a microcoded engine as the controller, which offers… (More)