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We have achieved aggressive reduction of V T variation and V DD-min by a sophisticated planar bulk MOSFET named 'Deeply Depleted Channel TM (DDC)'. The DDC transistor has been successfully integrated into an existing 65nm CMOS platform by combining layered channel formation and low temperature processing. The 2x reduction of V T variation in 65nm-node has(More)
The continued scaling of feature size has brought increasingly significant challenges to conventional optical lithography.[1-3] The rising cost and limited resolution of current lithography technologies have opened up opportunities for alternative patterning approaches. Among the emerging patterning approaches, block copolymer self-assembly for device(More)
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