Learn More
This paper describes the development of a synthesizable SoC platform using OpenCores processor and WISHBONE on-chip bus. The platform includes a OpenRISC 1200 microprocessor, some basic peripherals, such as on-chip RAM, GPIO, UART, debug interface, VGA controller and WISHBONE bus and uses the set of development environment including compiler, assembler,(More)
This paper presents a branch prediction algorithm and a 4-way set-associative cache for performance improvement of 32-bit RISC processor and a clock gating algorithm using ODC (observability don't care) operation for a low-power processor. The branch prediction algorithm has a structure using BTB (branch target buffer) and 4-way set associative cache using(More)
  • 1