Kwang-Sung Ma

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A 1.2 V 12 b 30 MS/s pipelined ADC, implemented in a 65 nm standard CMOS technology, achieves an SNDR of 65.1 dB with a rail-to-rail 4.7 MHz input. A capacitive reference scaling technique is proposed to alleviate the high gain requirement of the opamp and a wide input range of 2.4 Vp-p differential for low voltage operation in the nanometer domain. The(More)
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