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A 1.2 V 12 b 30 MS/s pipelined ADC, implemented in a 65 nm standard CMOS technology, achieves an SNDR of 65.1 dB with a rail-to-rail 4.7 MHz input. A capacitive reference scaling technique is proposed to alleviate the high gain requirement of the opamp and a wide input range of 2.4 Vp-p differential for low voltage operation in the nanometer domain. The(More)
—A novel 12 GHz VCO designed and fabricated in a 0.18 µm SiGe BiCMOS technology is presented. Strongly magnetic coupled dual LC tanks with fixed and tunable capacitive elements are introduced to extend tuning range and improve phase noise. By hybrid using of varactor tuning, loaded transformer tuning and switched capacitor tuning, the proposed VCO achieves(More)
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