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The theory of "parallel pathways" predicts that, except for a sign reversal, ON and OFF ganglion cells are driven by a similar presynaptic circuit. To test this hypothesis, we measured synaptic inputs to ON and OFF cells as reflected in the subthreshold membrane potential. We made intracellular recordings from brisk-transient (Y) cells in the in vitro(More)
Retinal ganglion cells adapt their responses to the amplitude of fluctuations around the mean light level, or the "contrast." But, in mammalian retina, it is not known whether adaptation arises exclusively at the level of synaptic inputs or whether there is also adaptation in the process of ganglion cell spike generation. Here, we made intracellular(More)
Hardware implementations of spiking neurons can be extremely useful for a large variety of applications, ranging from high-speed modeling of large-scale neural systems to real-time behaving systems, to bidirectional brain-machine interfaces. The specific circuit solutions used to implement silicon neurons depend on the application requirements. In this(More)
The goal of perception is to extract invariant properties of the underlying world. By computing contrast at edges, the retina reduces incident light i n tensities spanning twelve decades to a twentyfold variation. In one stroke, it solves the dynamic range problem and extracts relative reeec-tivity, bringing us a step closer to the goal. We h a ve built a(More)
We use neuromorphic chips to perform arbitrary mathematical computations for the first time. Static and dynamic computations are realized with heterogeneous spiking silicon neurons by programming their weighted connections. Using 4K neurons with 16M feed-forward or recurrent synaptic connections, formed by 256K local arbors, we communicate a scalar(More)
This paper describes the design of the first hardware system to provide computational neuroscientists with the capability of performing biological real-time simulations of a million neurons and their synaptic connections. ABSTRACT | In this paper, we describe the design of Neurogrid, a neuromorphic system for simulating large-scale neural models in real(More)
An 80 x 60 pixels arbitrated address-event imager has been designed and fabricated in a 0.6µm CMOS process. The value of the intensity is inversely proportional to the inter-spike interval and the read-out of each spike is initiated by the pixel. The available output bandwidth is allocated according to the pixel's demand, favoring brighter pixels and(More)
A retinal ganglion cell receptive field is made up of an excitatory center and an inhibitory surround. The surround has two components: one driven by horizontal cells at the first synaptic layer and one driven by amacrine cells at the second synaptic layer. Here we characterized how amacrine cells inhibit the center response of on- and off-center Y-type(More)
—We describe a neuromorphic chip designed to model active dendrites, recurrent connectivity, and plastic synapses to support one-shot learning. Specifically, it is designed to capture neural firing patterns (short-term memory), memorize individual patterns (long-term memory), and retrieve them when primed (associative recall). It consists of a recurrently(More)
—We present a transmitter for a scalable multiple-access inter-chip link that communicates binary activity between two-dimensional arrays fabricated in deep submicrometer CMOS. Transmission is initiated by active cells but cells are not read individually. An entire row is read in parallel; this increases communication capacity with integration density.(More)