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We present a protocol for determining the relative orientation and dynamics of A-form helices in 13C/15N isotopically enriched RNA samples using NMR residual dipolar couplings (RDCs). Non-terminal Watson-Crick base pairs in helical stems are experimentally identified using NOE and trans-hydrogen bond connectivity and modeled using the idealized A-form helix(More)
A novel DRAM cell technology consisting of an n-channel access transistor and a bootstrapped storage capacitor with an integrated breakdown diode is proposed. This design offers considerable resistance to single event cell errors. The informational charge packet is shielded from the single event by placing the vulnerable node in a self-compensating state(More)
A telescopic cascode opamp typically has a higher frequency capability and consumes less power than other topologies. The disadvantage of a telescopic opamp is severely limited output swing. In a conventional telescopic opamp shown in Figure 1, all transistors are biased in the saturation region. Transistors M1-M2, M7-M8 and the tail current source M9 must(More)
This paper proposes and investigates schemes for hardening the conventional CMOS cross-coupled DRAM sense amplifier to single event upset (SEU). These schemes, adapted from existing SRAM hardening techniques, are intended to harden the dynamic random access memory to bitline-mode errors during the sensing period. Simulation results indicate that a 9kΩ(More)
A 12-bit 200MS/s zero-crossing based pipeline ADC is presented. A coarse phase followed by a level-shifted fine phase is employed for higher accuracy. To enable high frequency operation, sub-ADC flash comparators are strobed immediately after the coarse phase. The ADC occupies 0.276mm<sup>2</sup> in 55nm CMOS and dissipates 28.5mW. 62.5dB SNDR and 78.6dBc(More)
—A low-power CMOS reconfigurable analog-to-digital converter that can digitize signals over a wide range of bandwidth and resolution with adaptive power consumption is described. The converter achieves the wide operating range by (1) reconfig-uring its architecture between pipeline and delta–sigma modes; (2) varying its circuit parameters, such as size of(More)
A 0.5V 1Msps track-and-hold (T/H) circuit with a 60dB SNDR is presented. The fully-differential circuit is implemented in a 0.25µm CMOS technology, with standard 0.6V VT devices, and uses true low voltage design techniques i.e. with no clock and no voltage boosting. This paper describes a ratio-independent algorithmic ADC architecture that requires a single(More)