Kush Gulati

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We present a protocol for determining the relative orientation and dynamics of A-form helices in 13C/15N isotopically enriched RNA samples using NMR residual dipolar couplings (RDCs). Non-terminal Watson-Crick base pairs in helical stems are experimentally identified using NOE and trans-hydrogen bond connectivity and modeled using the idealized A-form helix(More)
A novel DRAM cell technology consisting of an n-channel access transistor and a bootstrapped storage capacitor with an integrated breakdown diode is proposed. This design offers considerable resistance to single event cell errors. The informational charge packet is shielded from the single event by placing the vulnerable node in a self-compensating state(More)
A 12-bit 200MS/s zero-crossing based pipeline ADC is presented. A coarse phase followed by a level-shifted fine phase is employed for higher accuracy. To enable high frequency operation, sub-ADC flash comparators are strobed immediately after the coarse phase. The ADC occupies 0.276mm 2 in 55nm CMOS and dissipates 28.5mW. 62.5dB SNDR and 78.6dBc SFDR with a(More)
This paper proposes and investigates schemes for hardening the conventional CMOS cross-coupled DRAM sense amplifier to single event upset (SEU). These schemes, adapted from existing SRAM hardening techniques, are intended to harden the dynamic random access memory to bitline-mode errors during the sensing period. Simulation results indicate that a 9kΩ(More)
—A 12 bit 200 MS/s analog-to-digital converter (ADC) applies techniques of zero-crossing-based circuits as a replacement for high-gain high-speed op-amps. High accuracy in the residue amplifier is achieved by using a coarse phase in ZCBC followed by a level-shifting capacitor for fine phase. Sub-ADC flash com-parators are strobed immediately after the(More)
  • Todd C Sepke Jul, Todd C Sepke, Iliana Fujimori, Pablo M Acosta Serafini, Ginger Wang, Dan Mcmahill +5 others
  • 2014
This thesis is a study of noise in CMOS field effect transistors, and the effects of scaling on high frequency low noise circuit design. A graphical derivation of the intrinsic noise sources in a square-law MOSFET transistor that includes the drain noise current , the gate noise current, and their correlation is presented. In this derivation, the channel is(More)