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We present a protocol for determining the relative orientation and dynamics of A-form helices in 13C/15N isotopically enriched RNA samples using NMR residual dipolar couplings (RDCs). Non-terminal Watson-Crick base pairs in helical stems are experimentally identified using NOE and trans-hydrogen bond connectivity and modeled using the idealized A-form helix(More)
We examined how static and dynamic deviations from the idealized A-form helix propagate into errors in the principal order tensor parameters determined using residual dipolar couplings (rdcs). A 20-ns molecular dynamics (MD) simulation of the HIV-1 transactivation response element (TAR) RNA together with a survey of spin relaxation studies of RNA dynamics(More)
A novel DRAM cell technology consisting of an n-channel access transistor and a bootstrapped storage capacitor with an integrated breakdown diode is proposed. This design offers considerable resistance to single event cell errors. The informational charge packet is shielded from the single event by placing the vulnerable node in a self-compensating state(More)
This paper proposes and investigates schemes for hardening the conventional CMOS cross-coupled DRAM sense amplifier to single event upset (SEU). These schemes, adapted from existing SRAM hardening techniques, are intended to harden the dynamic random access memory to bitline-mode errors during the sensing period. Simulation results indicate that a 9kΩ(More)
—A low-power CMOS reconfigurable analog-to-digital converter that can digitize signals over a wide range of bandwidth and resolution with adaptive power consumption is described. The converter achieves the wide operating range by (1) reconfig-uring its architecture between pipeline and delta–sigma modes; (2) varying its circuit parameters, such as size of(More)
A 12-bit 200MS/s zero-crossing based pipeline ADC is presented. A coarse phase followed by a level-shifted fine phase is employed for higher accuracy. To enable high frequency operation, sub-ADC flash comparators are strobed immediately after the coarse phase. The ADC occupies 0.276mm<sup>2</sup> in 55nm CMOS and dissipates 28.5mW. 62.5dB SNDR and 78.6dBc(More)