Kurt Rosenfeld

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JTAG IS THE DOMINANT standard for in-circuit test. In use for 20 years, JTAG, like many mature standards for information systems, was conceived with a friendly environment in mind. It was designed to handle the natural enemies of digital systems: faults in design, fabrication, packaging, and PC boards. JTAG’s success has been largely due to the standard’s(More)
We propose a novel variety of sensor that extends the functionality of conventional physical unclonable functions to provide authentication, unclonability, and verification of a sensed value. This new class of device addresses the vulnerability in typical sensing systems whereby an attacker can spoof measurements by interfering with the analog signals that(More)
We present Volleystore, a filesystem that stores data on network equipment and servers without any authorization, yet without compromising the systems that are used. This is achieved by exploiting the echo functionality present in most standard Internet protocols. Various issues concerning the design of a parasitic storage system are addressed and a(More)
computer 64 Published by the IEEE Computer Society 0018-9162/11/$26.00 © 2011 IEEE a trusted design center and foundry, it is expensive and economically infeasible given current trends in the globalization of IC design and fabrication. On the other hand, verifying trustworthiness requires a postmanufacturing step to validate conformance of the fabricated IC(More)
We investigate the robustness of PRNU-based camera identification in cases where the test images have been passed through common image processing operations. A specific question we aim to answer is how camera identification can be circumvented by an nontechnical user, applying only standard and/or freely available software. We study denoising,(More)
Test access mechanisms are critical components in digital systems. They affect not only production and operational economics, but also system security. We propose a security enhancement for system-on-chip (SoC) test access that addresses the threat posed by untrustworthy cores. The scheme maintains the economy of shared wiring (bus or daisy-chain) while(More)
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