Kuo-Ning Chiang

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The flip chip packaging structure design and the fabrication process parameters will influence the packaging reliability and the performance of chip heat dissipation. The reliability of a flip chip package depends on the packaging structure design parameters, which include solder bump geometry, die side pad and substrate side pad dimensions, etc. In order(More)
By applying the etching via technology, this study proposes a novel front-side etching fabrication process for a silicon-based piezoresistive pressure sensor to replace the conventional backside bulk micro-machining. This novel structure pressure sensor can achieve the distinguishing features of the chip size reduction and fabrication costs degradation. In(More)
During the design and manufacturing processes of electronic packaging, solder joints are fabricated using a variety of methods to provide both mechanical and electrical connections for different applications. They include flip chip, wafer level chip scale packaging (WLCSP), fine pitch ball grid array (BGA), and chip scale packaging (CSP). The solder joint(More)
This investigation presents a detailed design procedure for a lead-free flip chip BGA package which includes solder bump profile prediction, FEM simulation, test vehicle design/fabrication and accelerated thermal cycle (ATC) testing to study the reliability issues of the flip chip packages. The solder joint reliability of a flip chip package depends on the(More)
Keywords: MEMS Piezoresistive pressure sensor Finite element method (FEM) Packaging effect a b s t r a c t The silicon-based pressure sensor is one of the major applications in the MEMS device. Nowadays, the silicon piezoresistive pressure sensor is a mature technology in the industry, but its requirement in terms of sensing accuracy and stability is more(More)
In this research, the objective is to develop a stress-buffer-enhanced package subjected to board level drop test under a high-G impact drop; both drop test experiments and ANSYS/LS-DYNA simulations are executed. Many researchers indicate that solder joints in wafer level chip scale package (WLCSP) are the weakest portion in board-level drop test because of(More)