Kuo-Ning Chiang

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By applying the etching via technology, this study proposes a novel front-side etching fabrication process for a silicon-based piezoresistive pressure sensor to replace the conventional back-side bulk micro-machining. This novel structure pressure sensor can achieve the distinguishing features of the chip size reduction and fabrication costs degradation. In(More)
As the industry keeps moving towards further miniaturization of electronic devices, even smaller sizes, a lower economical cost, and higher reliability are not only convenient but have become a necessity of the design. A well-designed package structure can effectively restrain the solder joint fatigue failure induced by material coefficient of thermal(More)
Recently, consumer electronics demand has been geared towards lightweight, high efficiency, and small form factor devices. These characteristics can be accomplished by using three-dimensional (3D) integrated circuit (IC) technology. This study proposes a double-chip stacking structure in an embedded fan-out wafer level packaging (WLP) with double-sided(More)
This investigation presents a detailed design procedure for a lead-free flip chip BGA package which includes solder bump profile prediction, FEM simulation, test vehicle design/fabrication and accelerated thermal cycle (ATC) testing to study the reliability issues of the flip chip packages. The solder joint reliability of a flip chip package depends on the(More)
During the design and manufacturing processes of electronic packaging, solder joints are fabricated using a variety of methods to provide both mechanical and electrical connections for different applications. They include flip chip, wafer level chip scale packaging (WLCSP), fine pitch ball grid array (BGA), and chip scale packaging (CSP). The solder joint(More)
In this research, the objective is to develop a stress-buffer-enhanced package subjected to board level drop test under a high-G impact drop; both drop test experiments and ANSYS/LS-DYNA simulations are executed. Many researchers indicate that solder joints in wafer level chip scale package (WLCSP) are the weakest portion in board-level drop test because of(More)