Kuo-Chun Hsu

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A novel native-NMOS-triggered SCR (NANSCR) is proposed for efficient ESD protection design in a 0.13-/spl mu/m CMOS process. As compared with the traditional LVTSCR, the trigger voltage, turn-on resistance, turn-on speed, and CDM ESD level of NAN SCR have been greatly improved to protect the ultra-thin gate oxide against ESD stresses. The proposed NANSCR(More)
A new power-rail electrostatic discharge (ESD) clamp circuit for application in 3.3-V mixed-voltage input-output (I/O) interface is proposed and verified in a 130-nm 1-V/2.5-V CMOS process. The devices in this power-rail ESD clamp circuit are all 1-V or 2.5-V low-voltage nMOS/pMOS devices, which are specially designed without suffering the gate-oxide(More)
A new design concept for on-chip electrostatic discharge (ESD) protection circuits with the already-on device is proposed to provide efficient ESD protection for ICs in nanoscale CMOS technologies. The already-on device used in this work is the native-NMOS-triggered SCR (NANSCR) device, which has a trigger voltage of almost zero in a 130-nm CMOS process.(More)
A novel design concept to turn on the SCR device by applying the substrate-triggered method is first proposed in the literature for effective on-chip ESD protection design. To avoid the transient-induced latch-up issue, the substratetriggered SCR devices are stacked in the ESD protection circuits. The turn-on efficiency of SCR can be greatly improved by(More)
Turn-on speed is the main concern for on-chip electrostatic discharge (ESD) protection device, especially in deep submicron complementary metal-oxide semiconductors (CMOS) processes with ultra-thin gate oxide. A novel dummy-gate-blocking silicon-controlled rectifier (SCR) device with substrate-triggered technique is proposed to improve the turn-on speed of(More)
A substrate-triggered technique is proposed to improve ESD protection efficiency of the stacked-NMOS device in the mixed-voltage I/O circuit. The substrate-triggered technique can further lower the trigger voltage of the stacked-NMOS device to ensure effective ESD protection for the mixed-voltage I/O circuit. The proposed ESD protection circuit with the(More)
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