Kunio Uchiyama

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Power efficient SoC design for embedded applications requires several independent power-domains where the power of unused blocks can be turned off. An SoC for mobile phones [1] defines 23 hierarchical power domains but most of the power domains are assigned for peripheral IPs that mainly use low-leakage high-Vt transistors. Since high-performance(More)
Frequency-voltage cooperative power control (FVC) is considered a powerful method to reduce the power consumption of a program, because it utilizes the information of software loads dynamically. The authors first show through a mathematical analysis that FVC with only two frequency-voltage sets is sufficient for current lowVdd CPU chips. Then we show an(More)
A heterogeneous multi-core processor (HMCP) architecture, which integrates general purpose processors (CPU) and accelerators (ACC) to achieve high-performance as well as low-power consumption with the support of a parallelizing compiler, was developed. The evaluation was performed using an MP3 audio encoder on a simulator that accurately models the HMCP. It(More)
The large data-transfer time among different cores is a big problem in heterogeneous multi-core processors. This paper presents a method to accelerate the data transfers exploiting data-transfer-units together with complex memory allocation. We used block matching, which is very common in image processing, to evaluate our technique. The proposed method(More)