Kuk-Tae Hong

Learn More
This paper describes a 10b 204MS/s analog-to-digital converter (ADC) employing a pipelined successive approximation register (SAR) architecture for low power consumption and small area. To improve the operation frequency, the pipelined SAR ADC consists of two channels with a proposed asynchronous timing technique. This technique increases the amplification(More)
This paper presents a digital PLL for low long-term jitter clock recovery. A jitter reduction scheme for digitally controlled oscillator is proposed and 39% jitter reduction is observed. A 5-phase digital phase frequency detector (PFD) has 265 ps resolution and controls output clock phase by 132 ps step. The long-term jitter is measured as 460 ps pk-pk.(More)
A fully integrated loop-through amplifier (LTA) for cable TV tuner is presented in a 0.18 mum CMOS process. It covers the whole frequency band from 48 MHz to 860 MHz and allows a second TV and multiple tuners. This circuit employs a parallel connection of common-gate and common-source (CG-CS) amplifiers for broadband matching. The performances are enhanced(More)
  • 1