Kugan Vivekanandarajah

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Filter cache (FC) is effective in achieving energy saving at the expense of some performance degradation. The energy savings, here, comes from repeated execution of tiny loops from energy efficient FC. The absence of cacheable loops leads to performance degradation in such FC structures. Therefore, we propose a simple dynamic FC scheme, which detects the(More)
Filter cache has been shown to substantially reduce the power consumption in instruction memory hierarchy. Filter cache achieves energy savings due to the locality found in the frequent tiny loops, which are application dependent. In this paper we show that tuning filter cache to the needs of a particular application can save power and energy. Beside, a(More)
This paper investigates automatic mapping of application-to-architecture in heterogeneous Multi Processor System on a Chip (MPSoC), a key problem in system level design of embedded systems. An algorithm is proposed to optimally solve this application-to-architecture mapping problem. The proposed algorithm uses efficient branch-and-bound approach to(More)
Cache memories improve the performance due to the locality found within the loops of application. Because these loop characteristics are application dependent, the optimal cache hierarchy for performance and energy saving is also application dependent. Traditionally, cache simulations are employed to tune the cache hierarchy. In this paper we propose a(More)
A filter cache is proposed at a higher level than the L1 (main) cache in the memory hierarchy and is much smaller. The typical size of filter cache is of the order of 512 Bytes. Prediction algorithms popularly based upon the Next Fetch Prediction Table (NFPT) helps making the choice between the filter cache and the main cache. In this paper we introduce a(More)
Filter cache (FC) is an auxiliary cache much smaller than the main cache. The FC is closest in hierarchy to the instruction fetch unit and it must be small in size to achieve energyefficient realisations. A pattern prediction scheme is adapted to maximise energy savings in the FC hierarchy. The pattern prediction mechanism proposed relies on the spatial hit(More)
The power consumption of microprocessors has been increasing in step with the complexity of each progressive generation. In general purpose processors, this is primarily attributed to the high energy consumption of fetch and decode circuitry, pursuant to the high instruction issue rate required of these high performance processors. Predictive Decode Filter(More)
Energy dissipation in cache memories is becoming a major design issue in embedded microprocessors. Predictive filter cache based instruction cache hierarchy is effective in reducing the access energy substantially at the cost of certain performance degradation. Here, the energy-delay product reduction heavily depends on the prediction accuracy of the(More)
Ultra-low power asynchronous processor designs for sensor networks have been proposed in recent research of the order of 17 pJ/ins for 0.6 V in a 180 nm CMOS process. All these processor designs are based on supporting only one simple radio software stack. The design optimization of such processors needs to be studied in the ultra-low power context for(More)
The pattern prediction algorithm has been shown in past research to provide substantial improvements in energy consumption, without sacrificing performance when used to predict access to the filter cache in the instruction memory hierarchy. Since, the pattern predictor and the filter cache are an overhead to the existing cache architecture, it is imperative(More)
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