Kuba Raczkowski

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A 4-antenna path beamforming analog baseband section implemented in 40 nm low power CMOS for use in a phased-array 60 GHz receiver is presented. The circuit combines fourth-order filtering with a cutoff frequency of 1 GHz, beamforming and variable gain between 10.6 dB and 30 dB. Output IP3 above 10 dBm and output noise below 4.2 mVrms over the whole gain(More)
For high-data-rate wireless communication in the 7GHz band around 60GHz, the IEEE 802.15.3c standard [1] provides channels with a 0.88GHz bandwidth for the AV-OFDM mode. For the single-carrier modes, the ECMA 387 standard [2] foresees the possibility of bonding together adjacent channels, yielding higher data-rates. Radios for these 60GHz standards often(More)
Research in recent years has shown that downscaled CMOS is a serious technology candidate to implement transceivers for high-data-rate wireless communication around 60GHz [1,2]. A low-cost implementation is the combination of the digital part with the transceiver onto a single chip. The complexity of the digital part demands a very advanced CMOS technology,(More)
Recently, 60GHz receiver front-ends have emerged, aiming for very high-datarate communication [1-4]. From a cost perspective, a highly integrated solution is favorable. Speed and power consumption considerations for the highdata-rate digital part of the chip make 45nm CMOS a very realistic candidate technology for such systems. This work presents a(More)
This paper describes a fractional-N subsampling PLL in 28 nm CMOS. Fractional phase lock is made possible with almost no penalty in phase noise performance thanks to the use of a 10 bit, 0.55 ps/LSB digital-to-time converter (DTC) circuit operating on the sampling clock. The performance limitations of a practical DTC implementation are considered, and(More)
We present a 60 GHz four-antenna phased-array direct conversion receiver in 90 nm RF CMOS with an LO based on subharmonic injection locking, beamforming that is partially in the LO path and partially at analog baseband, and an analog baseband section. The LO system features a set of four 60 GHz oscillators, locked to the fifth harmonic of a central(More)
This paper describes a fractional-N subsampling PLL in 28nm CMOS. Fractional lock is achieved by using a 10bit digital-to-time converter (DTC) that generates a delayed sampling clock with minimal impact on PLL performance. Background calibration guarantees appropriate DTC gain, reducing spurs. The system achieves -38 dBc of integrated phase noise (280fs RMS(More)