Krzysztof Sacha

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A method is described for modeling, verification and automatic generation of code for PLC controllers. The modeling of requirements and the implementation of code are based on a definition of a finite state time machine. The verification process uses UPPAAL, a model checking tool for the networks of timed automata. A conversion between both models is done(More)
The paper describes syntax, behavior and formal semantics of a new class of timed automata, which are tailored for modeling the behavior of real-time systems. A formal method for automatic generation of programs is developed around this model. The method starts from modeling the desired behavior of the system under design by means of a UML-based state(More)