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This paper presents two heuristics for automatic hardware/software partitioning of system level specifications. Partitioning is performed at the granularity of blocks, loops, subprograms, and processes with the objective of performance optimization with a limited hardware and software cost. We define the metric values for partitioning and develop a cost(More)
The work presented in this paper addresses minimization of the energy consumption of a system during system-level design. The paper focuses on scheduling techniques for architectures containing variable supply voltage processors, running dependent tasks. We introduce our new approach for Low-Energy Scheduling (LEneS) and compare it to two other scheduling(More)
This paper describes two methods to specify timing constraints in behavioral VHDL for high-level synthesis purposes. The first method specifies timing constraints on sequences of statements by using predejned procedures. The second method provides support for specification of timing constraints across process borders based on concurrent assert statements on(More)
We present an approach to process scheduling based on an abstract graph representation which captures both dataflow and the flow of control. Target architectures consist of several processors, ASICs and shared busses. We have developed a heuristic which generates a schedule table so that the worst case delay is minimized. Several experiments demonstrate the(More)
Most of the current methods for designing power/energy efficient digital systems are addressing either the system hardware or system software. This is usually performed quite late in the design process. This paper presents a method for minimizing the energy consumption at system level, early in the design process. Our approach to low-energy system design(More)
This paper presents an approach for system level specification and hardware/software partitioning with VHDL. The implications of using VHDL as a specification language are discussed and a message passing mechanism is proposed for process interaction. We define the metric values for partitioning and develop a cost function that guides our heuristics towards(More)
This paper presents a new constraint-driven method for fast identification of computational patterns that is a part of DURASE system (Generic Environment for Design and Utilization of Reconfigurable Application-Specific Processors Extensions). The patterns identified by our system form a base for application specific instruction selection and processor(More)