Kristian Fischer

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A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS.(More)
A 14nm logic technology using 2<sup>nd</sup>-generation FinFET transistors with a novel subfin doping technique, self-aligned double patterning (SADP) for critical patterning layers, and air-gapped interconnects at performance-critical layers is described. The transistors feature rectangular fins with 8nm fin width and 42nm fin height, 4<sup>th</sup>(More)
Interconnect process features are described for a 45nm high performance logic technology. Through extensive use of highly manufacturable carbon doped oxide low-k dielectric layers and aggressive scaling of the SiCN etch stop film the Metal-1 to Metal-8 interconnect stack demonstrates a 10% average capacitance reduction over the 65nm process. The(More)
We describe here Intel's 14nm high-performance logic technology interconnects and back end stack featuring 13 metal layers and a tri-metal laminated metal-insulator-metal (MIM) capacitor. For the first time on a logic product in high volume, multiple layers (M4 and M6) incorporate an air gap integration scheme to deliver up to 17% RC benefit. Pitch Division(More)
The Munich Simulation Computer (MuSiC), a special-purpose, highly-parallel programmable machine, is an approach to transfer concepts (developed for data flow computers) to fast, mixed-design-level simulation of digital systems. To gain high performance, however, the operation principle is modified from data flow computation to event flow computation. This(More)
Coming along with the spread of location-independent wireless networks and attractive mobile devices like “smartphones” or “pads”, activities in the Web increasingly take place in volatile mobile environments, even if sensitive information objects are involved. In this paper a approach is proposed to apply security measures to such objects in a context(More)
We describe here performance enhancement to Intel's 14nm high-performance logic technology interconnects and back end stack and introduce the SOC technology family of interconnects. Enhancement includes improved RC performance and intrinsic capacitance for back end metal layers over a range of process versions and metal stacks offered for optimal cost and(More)
A prototype X.400 message handling system for IBM's VM/SP operating system is discussed. The system is designed to provide smooth integration of X.400 services into the predominantly used means of interpersonal communication in the VM/SP environment (RSCS). The system provides native X.400 services to its users and therefore is not a gateway between RSCS(More)