Krishnan Ravichandran

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A graphics execution core in 22nm improves energy efficiency across a wide DVFS range, from the near-threshold voltage (NTV) region, where circuit assist lowers intrinsic VMIN, to the turbo region, where adaptive clocking reduces the voltage-droop guard-band [1]. When powered with a shared rail, however, energy is wasted in the core if other blocks demand(More)
A fully on-die, digitally controlled, 500MHz switching, 250mA rated output buck Voltage Regulator (VR) implemented in 22nm Tri-Gate CMOS is presented. The silicon measured a peak efficiency of 68% and consumed an area of 0.6mm 2 (without output decoupling) with a power density of about 410 mW/mm 2 . The paper also demonstrates a controller bandwidth of(More)
Active conduction modulation techniques are demonstrated in a fully integrated multi-ratio switched-capacitor voltage regulator with hysteretic control, implemented in 22nm tri-gate CMOS with high-density MIM capacitor. We present (i) an adaptive switching frequency and switch-size scaling scheme for maximum efficiency tracking across a wide range voltages(More)
A monolithic microwatt-level charge pump energy harvester is proposed for smart nodes of Internet of Things (IOT) networks. Due to the variation of the available voltage and power in IOT scenarios, the charge pump was optimized by the proposed architecture and circuit level innovations. First, a reconfigurable charge pump is introduced to provide the hybrid(More)
Monolithic integration of Voltage Regulators (VR) is challenging given the inherent lack of scalability of inductor. Circuit techniques to reduce inductor size are attractive to increase power density and scalability. This paper presents a 70~72% efficient, 500MHz digitally controlled 3-level Buck VR with a fully on-die spiral inductor implemented on 22nm(More)
Mobile PC platforms enabled with Intel CentrinoTM mobile technology incorporate innovative technologies to significantly increase the mobility of notebook PCs. In this paper, we describe the following innovations: • How to reduce interference between wireless communication technologies using the Intel Wireless Coexistence System (Intel WCS). • Two(More)
Integrated buck VR designs with different types of power inductor integration technologies have been reported [1-3]. In [1], planar lateral coupled power inductors with non-planar magnetic cores for higher inductance, quality factor and current density, are integrated on a separate silicon interposer die which is then wirebonded to the VR die on a common(More)