Krishnamoorthy Raja

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The paper presents a new spike detector proposed for the Neuromodulation SoC. The SoC designed combines the 64 acquisition channels with digital compression and simulation. The objective of this work is to design a spike detector for event detector. In literature several designs available which uses above 90nm technology with supply voltage greater than(More)
The objective of the work is to design a new clock gated based flip flop for pipelining architecture. In computing and consumer products, the major dynamic power is consumed in the system’s clock signal, typically about 30% to 70% of the total dynamic (switching) power consumption. Several techniques to reduce the dynamic power have been developed, of which(More)
The paper presents a low power ECG signal processing ASIC chip design to extract the ECG features for wearable health system. The new design is used for the diagnosis of ECG arrhythmia based on features. The design consists of an acquisition unit, analog to digital conversion, pre-processing stage and feature extraction stage. The proposed design is(More)
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