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This paper proposes a new architecture for VASA, a single-chip MPEG-2 422P@HL CODEC LSI with multi-chip configuration for large scale processing beyond the HDTV level, and demonstrates its flexibility and usefulness. This architecture consists of triple encoding cores, a decoding core, a multiplexer/de-multiplexer core, and several dedicated(More)
This paper proposes a new architecture for a single-chip MPEG-2 video encoder with scalability for HDTV and demonstrates its flexibility and usefulness. The architecture based on three-layer cooperation provides flexible data-transfer that improves the encoder from the standpoints of versatility, scalability, and video quality. The LSI was successfully(More)
We describe a multiple reference and multiple block size motion estimation (ME) hardware design for professional encoder LSIs, that supports H.264/AVC High 4:2:2 profile, MPEG-2 4:2:2 profile and MPEG-4. An 8x8-based “telescopic” integer motion estimation (IME) followed by an “inclusive” variable block size fractional motion estimation (FME) results in a(More)
The transform unit (TU), combining with the rate-distortion optimized quantization (RDOQ), as a part of the important features of HEVC brings much performance gain by adding more computation burden to the encoder. Different from the previous standards, the transform and quantization (T&Q) lead into a quadtree structure which requires to be split and(More)
SUMMARY This paper presents an architecture for a single-chip MPEG-2 video encoder and demonstrates its flexibility and usefulness. The architecture based on three-layer cooperation provides flexible data-transfer that improves the encoder from the standpoints of versatility, scalability, and video quality. The LSI was successfully fabricated in the 0.25-µm(More)
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