Kosei Okamoto

  • Citations Per Year
Learn More
The architecture of the TX3 implementation of the TRON-CHIP32 specification is discussed. TX3 supports the full instruction set, including the decimal, floating-point, and other complex instructions. Average performance above 10-MIPS is expected. This performance level is obtained by the use of an 8-kB instruction cache, 8-kB data cache, decoded instruction(More)
  • 1