Konstantinos Sarrigeorgidis

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We designed and implemented an ultra low power CORDIC processor which targets the implementation We propose a modified CORDIC algorithm and architecture. and we elaborate on the low power architectural and algorithmic techniques for minimizing its power consumption. Our CORDIC implementation consumes. in rotate mode, on average 50 Jl, W @ 10 MHz under 1 V(More)
We propose a massively parallel recongurable processor architecture targetted for the implementation of advanced wireless communication algorithms that feature matrix computations. A design methodology for programming and conguring the processor architecture is developed. The design entry point is the space representation of the algorithm in Simulink. The(More)
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