Konstantinos Sarrigeorgidis

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We propose a massively parallel recon gurable processor architecture targetted for the implementation of advanced wireless communication algorithms that feature matrix computations. A design methodology for programming and con guring the processor architecture is developed. The design entry point is the space representation of the algorithm in Simulink. The(More)
We designed and implemented an ultra low power CORDIC processor which targets the implementation We propose a modified CORDIC algorithm and architecture. and we elaborate on the low power architectural and algorithmic techniques for minimizing its power consumption. Our CORDIC implementation consumes. in rotate mode, on average 50 Jl, W @ 10 MHz under 1 V(More)
This paper presents a fully integrated GPS receiver with 2.4 dB NF, 1.2mm<sup>2</sup> area, and 13 mA of current in 55 nm CMOS. NF degrades by only 0.1/0.5/0.1 dB in the presence of GSM, DCS, and WiFi blockers respectively. By using current mode operation, push-pull topology, current reuse techniques, and modular Gm-TIA stages, area is about half and power(More)
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