Konstantina Karagianni

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ÐTwo VLSI architectures for the computationally efficient implementation of the elementary 3D geometrical transformations are introduced. The first one is based on a single floating-point multiply/add unit, while the other one comprises a four processingelement vector unit. By exploiting the structure of the elementary transformation matrices, some of the(More)
This paper investigates the impact of finite word length effects on the realization of a quasi-Newton frequency-domain channel equalizer. The performance is studied assuming fixed-point twopsilas complement implementation. Furthermore, an approximate rounding scheme is proposed which achieves hardware reduction when compared to rounding. Experimental(More)
The impact or a modified saturated arithmetic on power dissipation and signal quality produced by building blocks of a multicarrier modem is studied in this paper. The proposed simplified saturation scheme is shown to significantly reduce the switching activity of the arithmetic circuits, while it requires reduced hardware complexity for its implementation.(More)
VLSI implementation issues in the design of a parallel processor for the solution of a set of Navier-Stokes (NS) equations which model the flow of blood through a stenosis are discussed in this paper. Specifically, the Navier-Stokes equations and the Poisson equation are used for the calculation of the velocities and pressure of the blood in the stenosis.(More)
In this paper a finite word length analysis of the EBA-DFE is presented. It is shown that moderate word lengths are required, facilitating the hardware implementation of EBA-DFE. Both truncation and rounding schemes are studied for product quantization. Furthermore, a simplified approximate rounding scheme is proposed. It is shown that the proposed scheme(More)
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