Konstantin Septinus

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This paper presents a scalable massively parallel CRC architecture for high-speed network processing. The proposed method considers wide data busses, which result in highest throughput. In addition, data streams are processed without interrupts. An investigated 65nm-ASIC implementation example for 32-bit CRC encoding operates on 58 GBps data streams at(More)
This paper presents our experiences and describes the details of a project-oriented ASIC design course held at Leibniz University Hannover. Our approach for this curriculum is to bring a real project (AVR instruction compatible microcontroller) into the classroom and introduce a professional standard cell based chip-design to the students. Moreover, the(More)
In this paper we discuss a new architecture, which is deployed for multi-standard packet inspection and basic network processing tasks in a high-performance network coprocessor. Thereby, concepts, architecture, compiler tool-chain and VLSI area estimation for this programmable finite state machine based (FSM-based) Processing Engine, FPE, are presented. The(More)
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