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Area-optimized design of SOT-MRAM
Modeling Application-Level Soft Error Effects for Single-Event Multi-Bit Upsets
TLDR
We present a new estimation model that predicts the resulting error resilience levels for flip-flop MBU cases. Expand
Minimal Aliasing Single-Error-Correction Codes for DRAM Reliability Improvement
We discuss the problem of finding a minimal aliasing code among a class of systematic single-error-correction codes that are suitable to be implemented within DRAM die, as opposed to external ECCExpand
Efficient CTC interleaver and deinterleaver for the WiMAX standard
TLDR
This paper presents an interleaving and de-interleaving architecture for efficient CTC decoding for the WiMAX standard. Expand