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Optimizing the DRAM refresh count for merged DRAM/logic LSIs
In merged DRAM/logic LSIs, the DRAM portion could suffer from shorter data retention time because of heat and noise caused by the logic portion. Frequent refreshes increase power consumption. Also,Expand
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Dynamically variable line-size cache exploiting high on-chip memory bandwidth of merged DRAM/logic LSIs
This paper proposes a novel cache architecture suitable for merged DRAM/logic LSIs, which is called "dynamically variable line-size cache (D-VLS cache)". The D-VLS cache can optimize its line-sizeExpand
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  • 1
  • Open Access
High bandwidth, variable line-size cache architecture for merged DRAM/Logic LSIs
Merged DRAM/logic LSIs could provide high on-chip memory bandwidth by interconnecting logic portions and DRAM with wider on-chip buses. For merged DRAM/logic LSIs with the memory hierarchy includingExpand
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A high-performance/low-power on-chip memory-path architecture with variable cache-line size
SUMMARYThis paper proposes an on-chip memory-path architectureemploying the dynamically variable line-size (D-VLS) cache forhigh performance and low energy consumption. The D-VLScache exploits theExpand
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Dynamically Variable Line-Size Cache Architecture for Merged DRAM/Logic LSIs
SUMMARY This paper proposes a novel cache architecture suitable for merged DRAM/logic LSIs, which is called “dynamically variable line-size cache (D-VLS cache).” The D-VLS cache can optimize itsExpand
  • 5
  • Open Access
Performance/Energy Efficiency of Variable Line-Size Caches for Intelligent Memory Systems
Integrating main memory (DRAM) and processors into a single chip, or merged DRAM/logic LSI, makes it possible to exploit high on-chip memory bandwidth by widening on-chip bus and on-chip DRAM array.Expand
  • 3
  • Open Access
High-Performance/Low-Power Cache Architectures for Merged DRAM/Logic LSIs
Integrating main memory and microprocessors into the same chip is one of the most important technologies for future SOC (System-On-a-Chip). The integration makes it possible to realize novel memoryExpand
Cache memory device with variable block sizes mechanism
Cache memory device comprising a cache memory (100), provided to temporarily store data that is stored in a main memory (106), and a processor (130) that accesses the cache memory, comprising: -Expand
Prospective Silicon Applications and Technologies in 2025
Today, practical semiconductor products are an integral part of our lives and the infrastructure of society, and this trend will continue in the future. New areas of application will expand intoExpand
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  • Open Access