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SUMMARY This paper proposes a new architecture for multibit complex bandpass ∆ΣAD modulators with built-in Switched-Capacitor (SC) circuits for application to Low-IF receivers such as used for Bluetooth and WLAN. In the realization of complex bandpass ∆ΣAD modulators, we face the following problems: (i) SNR of AD converter is deteriorated by mis-matches(More)
A complementary half swing architecture is proposed for the high speed and low power bus operation. The bus is composed from a pair of lines. Each bus line within a pair utilizes the upper or lower half of the supply voltage exclusively. The architecture is applied to an embedded SRAM of the 0.5µm CMOS ATM switch LSI. Simulation results indicate that it(More)
— A second-order multi-bit switched-capacitor complex bandpass ∆ΣAD modulator has been designed and fabricated for application to low-IF receivers in wireless communication systems such as Bluetooth and WLAN. We propose a new structure of a complex bandpass filter in forward path with I, Q dynamic matching which is equivalent to the conventional one but it(More)
SUMMARY We have designed, fabricated and measured a second-order multibit switched-capacitor complex bandpass ∆ΣAD modulator to evaluate our new algorithms and architecture. We propose a new structure of a complex bandpass filter in the forward path with I, Q dynamic matching , that is equivalent to the conventional one but can be divided into two separate(More)
SUMMARY This paper describes a new floating-point divider (FDIV), in which the key features of redundant binary circuits and an asynchronous clock scheme reduce the delay time and area penalty. The redundant binary representation of +1 = (1, 0), 0 = (0, 0),-1 = (0,1) is applied to the all mantissa division circuits. The simple and unified representation(More)