Koichiro Mashiko

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SUMMARY This paper describes a new floating-point divider (FDIV), in which the key features of redundant binary circuits and an asynchronous clock scheme reduce the delay time and area penalty. The redundant binary representation of +1 = (1, 0), 0 = (0, 0),-1 = (0,1) is applied to the all mantissa division circuits. The simple and unified representation(More)
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