Koichiro Ishibashi

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In this paper, we proposed a soft-error hardened latch (SEH-latch) scheme that has an error correction function in the fine process. To achieve this, we designed two types of SEH-latch circuits and a standard latch circuit using 130 nm 2-well, and also 90 nm 2-well CMOS processes. The proposed circuit demonstrated 2-order higher immunity through a radiation(More)
A decoupling circuit using an operational amplifier is proposed to suppress substrate crosstalk in mixed-signal system-on-chip (SoC) devices. It overcomes the parasitic inductance problem of on-chip capacitor decoupling. The effect of the proposed decoupling circuit is not limited by parasitic fine impedance. A 0.13-/spl mu/m CMOS test chip showed that(More)
Asymmetric three-Tr. cell (ATC) DRAM which has one P-and two N-MOS transistors for one unit cell is proposed with "forced feedback sense amplifier" and "write echo refresh". Memory array of ATC DRAM operates at 0.5V and use only logic process with no additional process. A test chip on 90 nm technology dissipates 180 /spl mu/A in refresh current at 1 /spl(More)
In a speed-adaptive threshold-voltage CMOS (SA-Vt CMOS) circuit, the substrate bias is controlled so that delay in the circuit stays constant. Distributions of device speeds are squeezed under fast-operation conditions. With a ring oscillator using 0.25-µm CMOS devices as a test circuit, we found that the worst-case operating frequency was improved(More)
A cosmic-ray immune latch circuit is presented. The storage node is separated into three electrodes, and the soft error on one node can be corrected by the other two, even if there is a large and long-lasting influx of radiation-induced charges. The circuit is proved to have significant tolerance by utilizing a test chip.
We propose a method of reducing substrate noise and random fluctuations utilizing a self-adjusted forward body bias (SA-FBB) circuit. To achieve this, we designed a test chip that contained an on-chip oscilloscope for detecting dynamic noise from various frequency noise sources, and another test chip that contained 10-M transistors for measuring random(More)
6T-SRAM cells in the sub-100 nm CMOS generation are now being exposed to a fatal risk that originates from large local Vth variability (/spl sigma//sub v/spl I.bar/Local/). To achieve high-yield SRAM arrays in presence of random /spl sigma//sub v/spl I.bar/Local/ component, we propose worst-case analysis that determines the boundary of the stable Vth region(More)
A fast transient-response digital low-dropout (LDO) voltage regulator comprising only low-voltage MOS transistors was developed. The input voltage can be higher than the withstand voltage of the low-voltage MOS transistors by the proposed withstand-voltage relaxation scheme. The switching frequency of 1 GHz can be achieved using small-dimension low-voltage(More)
We have developed a fully logic-MOS-transistor designed on-chip digitally controlled LDO in 40 nm CMOS. The proposed TDC-based voltage sensor used as an ADC can reduce the offset error almost to zero. The area of this LDO with no analog circuits is only 0.057 mm<sup>2</sup>. To suppress the AC voltage drop due to large load transient (LLT), we developed a(More)
A 1.2-V calibration comparator array for a flash-type ADC has been developed using 0.13/spl mu/m generic CMOS technology. The developed offset calibration technique corrects the offset mismatch better than 6bit resolution. By employing an offset calibration circuit in the comparator array, the comparator array can operate at low supply voltages. To evaluate(More)