Klaus Hering

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The partitioning of complex processor models on the gate and register-transfer level for parallel functional simulation based on the clock-cycle algorithm is considered. We introduce a hierarchical partitioning scheme combining various partitioning algorithms in the frame of a competing strategy. Melting together different partitioning results within one(More)
Parallelization of VLSI-simulation exploiting model-inherent parallelism is a promising way to accelerate veri¯cation processes for whole processor designs. Thereby partitioning of hardware models in°uences the e±ciency of following parallel simulations essentially. Based on a formal model of Parallel Cycle Simulation we introduce partition valuation(More)
Cycle-based simulation at RT-and gate level realized by a Levelized Compiled Code (LCC) technique represents a well established method for functional verification in processor design. We present a parallel LCC simulation system developed to run on loosely-coupled processor systems allowing significant simulation acceleration. It comprises three parallel(More)
The partitioning of complex processor models on the gate and register-transfer level for parallel functional simulation based on the clock-cycle algorithm is considered. We introduce a hierarchical partitioning scheme combining various partitioning algorithms in the frame of a competing strategy. Melting together the di®erent partitioning results within one(More)
Brain metastases are major complications of common cancers. Tumor type and proneness to the CNS are thought to define the number and size of brain metastases. It is not known if intrinsic vascular factors can also have an effect. Restricted perfusion due to cerebral small vessel disease is frequent in elderly patients and causes white matter lesions (WML).(More)