Kiyoshi Shibayama

  • Citations Per Year
Learn More
This paper describes the architecture of a dynamically microprogrammable computer with low-level parallelism, called QA-2, which is designed as a high-performance, local host computer for laboratory use. The architectural principle of the QA-2 is the marriage of high-speed, parallel processing capability offered by four powerful Arithmetic and Logic Units(More)
We proposed a computer with low-level parallelism as one of the basic computer architectures and built a large scale experimental system called QA-2. By low-level parallelism, we mean that a long-word instruction controls simultaneously many ALUs, busses, registers and memories in a mode of fine-grained parallelism. The QA-2 employs a 256-bit instruction by(More)
In this paper, we propose a distributed storage system which relocates data blocks autonomously among the storage nodes. In the system which is composed of heterogeneous storage nodes, there are performance gaps among the storage devices. The storage tiers are made by such gaps in the system. When frequently accessed data blocks are placed on improper(More)
Transactional Memory (TM) is promising to make parallel programming easier. There have been many hardware implementations of transactional memory (HTM) proposed to improve the performance, but they still suffer from some overheads when a transaction commits or aborts. So, we have been developing a novel new HTM design, called DCTM, which enables(More)
We had proposed a distributed storage system which relocates data blocks autonomously among the storage nodes. Generally, owing to requirement of exchanging the management information frequently, such autonomous block migration tends to increase network traffic. Our previous work has presented a scheme to reduce network traffic by appending the management(More)
We have been developing a multiprocessor architecture which creates speculative threads from a sequential program and executes them in parallel. In this architecture, we aim at the large-scale speculation which supports the execution of speculative threads of arbitrary size and duration. So, our system must be able to analyze the dependency on large amounts(More)
In this paper, we present an e-learning back-end system which cooperates with a learning management system (LMS). Our back-end system is aimed at fair and effective assessment in a class of elementary programming practice. While most LMSs provide basic functions to support various learning courses, this back-end system complements such conventional LMSs by(More)
In this paper, we propose a new Hardware Transactional Memory (HTM) system for a shared-memory multiprocessor in which elementary processors are connected by a single common bus. One of the key features of our system is a modified snoop cache protocol to reduce overheads on the transactional memory consistency control. By publishing all of modified data in(More)