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Data retention time for ultimate DRAMs with an extremely scaled-down cell size has been investigated. The entire memory cells can be discretely categorized by two groups: leaky cells or normal cells, and the main distribution representing the normal cells shows longer than 40 s of the mean retention time. The leaky cells are mainly originated by(More)
A new MLC NAND page architecture is presented as a breakthrough solution for sub-40-nm MLC NAND flash memories and beyond. To reduce cell-to-cell interference which is well known as the most critical scaling barrier for NAND flash memories, a novel page architecture including temporary LSB storing program and parallel MSB program schemes is proposed. A BL(More)
A 512 Mb diode-switch PRAM has been developed in a 90 nm CMOS technology. The vertical diode-switch using the SEG technology has achieved minimum cell size and disturbance-free core operation. A core configuration, read/write circuit techniques, and a charge-pump system for the diode-switch PRAM are proposed. The 512 Mb PRAM has achieved read throughput of(More)
Numerous candidates attempting to replace Si-based flash memory have failed for a variety of reasons over the years. Oxide-based resistance memory and the related memristor have succeeded in surpassing the specifications for a number of device requirements. However, a material or device structure that satisfies high-density, switching-speed, endurance,(More)
A novel SONOS structure of SiO/sub 2//SiN/Al/sub 2/O/sub 3/ (SANOS) with TaN metal gate is for the first time proposed for the next generation non-volatile memory technology. When TaN metal gate is applied for the SANOS instead of commonly used n+ poly-Si, the unwanted backward Fowler-Nordheim tunneling current of electrons through the top oxide is(More)
Unlike graphene, the existence of bandgaps (1-2 eV) in the layered semiconductor molybdenum disulphide, combined with mobility enhancement by dielectric engineering, offers an attractive possibility of using single-layer molybdenum disulphide field-effect transistors in low-power switching devices. However, the complicated process of fabricating(More)
Despite several years of research into graphene electronics, sufficient on/off current ratio I(on)/I(off) in graphene transistors with conventional device structures has been impossible to obtain. We report on a three-terminal active device, a graphene variable-barrier "barristor" (GB), in which the key is an atomically sharp interface between graphene and(More)
We demonstrate resistive random access memory (RRAM) architecture with bi-layered switching element for reliable resistive switching memory. Based on the modulated Schottky barrier modeling, several key functions to achieve a realiable bipolar switching property are extracted. Our device shows an excellent memory performance such as enduracne of(More)
Highly manufacturable 64Mbit PRAM has been successfully fabricated using N-doped Ge/sub 2/Sb/sub 2/Te/sub 5/ (GST) and optimal GST etching process. Using those technologies, it was possible to achieve the low writing current of 0.6 mA and clear separation between SET and RESET resistance distributions. The 64Mb PRAM was designed to support commercial NOR(More)
A 5-Gb/s/pin transceiver for DDR memory interface is proposed with a crosstalk suppression scheme. The proposed transceiver implements a staggered memory bus topology and a glitch canceller to suppress crosstalk-induced distortions in a memory channel. The transceiver is implemented using 0.18 mum CMOS process and operates at 5 Gb/s. The results demonstrate(More)