Kimiyoshi Usami

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This potpet describes a rechnique to reduce po-lrithout <bollging circuit~ by molting ... o! two ••pply 110luges. OatH oh' ohe criticil pach ate run at the IO\Io'et supply to ..Wuoe powu. T() m.lnlnliz.c th.¢ t~umber of ino:rfacing lcvel-collvencn n~d. our algorithm duMeta tile citcurt~ which oper~e at redt.IC'Cd voluge.le.&ding IOtlusmted ''Oha8¢ scallng(More)
Leakage power dissipation becomes a dominant component in operation power in nanometer devices. This paper describes a design methodology to implement runtime power gating in a fine-grained manner. We propose an approach to use sleep signals that are not off-chip but are extracted locally within the design. By utilizing enable signals in a gated clock(More)
We present a low-power design method that utilizes the multiple supply voltages. The proposed method reduces the power consumption of random logic circuits by 47% on the average, with up to 15% area overhead, by the combination of “clustered Voltage Scaling (CVS) scheme” and “Bow by Row optimized Power &pply (RRPS) scheme”. By the CVS scheme, the optimal(More)
This paper describes a fully automated low-power design methodology in which three different voltage-scaling techniques are combined together. Supply voltage is scaled globally, selectively, and adaptively while keeping the performance. This methodology enabled us to design an MPEG4 codec core with 58% less power than the original in three week(More)
This paper proposes the ultrafine-grained run-time power gating of on-chip routers, in which the power supply to each router component (e.g., virtual-channel buffer, virtual-channel multiplexer, and crossbar multiplexer and output latch) can be individually controlled based on the applied workload. Since only the router components that are transferring a(More)
We have developed a function-level power estimation methodology for predicting the power dissipation of embedded software. For a given microprocessor core, we empirically build the &#8220;power data bank&#8221;, which stores the power information of the built-in library functions and basic instructions. To estimate the average power of an embedded software(More)
This paper describes an automated design technique to selectively use multi-threshold CMOS (MTCMOS) in a cell-by-cell fashion. MT cells consisting of low-Vth transistors and high-Vth sleep transistors are assigned to critical paths, while high-Vth cells are assigned to non-critical paths. Compared to the conventional MTCMOS, the gate delay is not affected(More)
A fine-grain dynamic power gating is proposed for saving the leakage power in MIPS R3000 by sleep control and applied to a processor pipeline. An execution unit is divided into four small units: multiplier, divider, shifter and other (CLU). The power of each unit is cut off dynamically, based on the operation. We tape-outed the prototype chip Geyser-0,(More)