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The well-known two-capacitor problem, in which exactly half the stored energy disappears when a charged capacitor is connected to an identical capacitor, is discussed based on the mechanical harmonic oscillator model approach. In the mechanical harmonic oscillator model, it is shown first that exactly half the work done by a constant applied force is(More)
The time variable electrical characteristics of pentacene thin-film transistors (TFTs) with poly(4-vinylphenol) gate dielectrics were investigated under various relative humidity conditions and the effect of moisture on the hysteresis behavior of the pentacene TFTs was studied. One possible cause of the hysteresis behavior is the presence of inherent(More)
In this work, we have fabricated TIPS-pentacene TFTs with conductive polymer (3,4-ethylenedioxythiophene):poly(4-stylenesulfonate) (PEDOT:PSS) source/drain electrodes which is patterned by maskless laser direct patterning (LDP). The 5-microm resolution of source and drain patterns with PEDOT:PSS were clearly defined. Furthermore, the OTFTs with 10-microm(More)
We used micro contact printing (micro-CP) to fabricate inverted coplanar pentacene thin film transistors (TFTs) with 1-microm channels. The patterning of micro-scale source/drain electrodes without etch process was successfully achieved using Polydimethylsiloxane (PDMS) elastomer stamp. We used the Ag nano particle ink as an electrode material, and the(More)
The sub-50 nm templates are successfully fabricated using hydrogen silsesquioxane (HSQ) and silicon nitride on silicon substrate. The HSQ template is directly patterned by e-beam direct writing. The cured HSQ pattern is used for the template of nanoimprint process. The silicon nitride template is reactively ion etched by ZEP resist mask pattern which is(More)
We demonstrated the feasibility of metal and dielectric liners using a solution process for deep trench capacitor application. The deep Si trench via with size of 10.3 microm and depth of 71 microm were fabricated by Bosch process in deep reactive ion etch (DRIE) system. The aspect ratio was about 7. Then, nano-Ag ink and poly(4-vinylphenol) (PVPh) were(More)
In this study, we present a spacer patterning technology for sub-30 nm gate template which is used for nano-scale MOSFETs fabrication. A spacer patterning technology using a poly-silicon micro-feature and a chemical vapor deposition (CVD) SiO2 spacer has been developed, and the sub-30 nm structures by conventional dry etching and chemical mechanical(More)
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