Kihwan Seong

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The transmitter driver and the data recovery circuit of receiver for 480 Mbps USB2.0 interface were designed with Verilog and synthesized to enhance design portability. The transmitter driver was implemented by using multiple tri-state inverter cells to generate a 0 ~ 400 mV swing for normal operation and a 0 ~ 800 mV swing for chirp operation. The data(More)
There continue to be efforts to develop methodologies for fully automated digital design of key analog building blocks. The phase-locked loop (PLL) is a block for which an all-digital implementation has been sought recently. There have been several approaches for fully synthesized digital PLLs [1–4] via gate-level implementation of a digitally(More)
An all-synthesizable current-mode transmitter driver for a USB2.0 high-speed (480 Mb/s) interface was proposed to enhance the design portability. The proposed driver was implemented using tristate inverter cells. It uses the differential current-mode architecture, with variable output voltage swing, and includes a predriver. It was also successfully applied(More)
A high-speed transmitter for serial link interface was synthesized by using only Verilog codes and digital standard cells. The transmitter employs a differential voltage-mode architecture with a 2-tap feed-forward equalizer (FFE). A delay line which is locked to a data period is used for the FFE operation because a high speed flip-flop is not available in(More)
An ECG monitoring system is implemented by using an android smart phone, an FPGA chip, a comparator, a resistor, a capacitor and an ECG front-end amplifier circuit. The FPGA chip includes a digital circuit block for delta modulator and a USB 1.1 PHY/LINK. The digital circuit block for delta modulator includes a sampler(D flip-flop), a sinc filter and a FIR(More)
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