Khushbu Chandrakar

We don’t have enough information about this author to calculate their statistics. If you think this is an error let us know.
Learn More
Researchers believe that the power reduction at the earliest stages of the system design process will have higher impacts on the final result. Multiple supply voltage design is broadly acknowledged as a compelling approach to reduce the power consumption of a CMOS circuit. A SAT-based approach which targets operation scheduling with varying voltages and(More)
In today's circuit designs, with increasing density of devices and fast augmentation of clock frequencies, low-power design is a crucial issue. Clock power devours 60-70 percent of aggregate chip power. This is because power is directly proportional to voltage and also the frequency of the clock when the modules are unused. The purpose of this work is to(More)
Today low power implementation in the modern system on chips requires a holistic and concurrent approach which includes collaboration between power modeling and software hardware co-design. Power gating is one of the emerging low power design techniques used in all the portable devices. The main goal of power gating is to eliminate the leakage current in(More)
The call for low power consumption has necessitated a paradigm shift with respect to circuit designing in which minimizing power consumption is as important as optimizing performance and area. A SAT based approach which targets operation scheduling and binding simultaneously and produces a circuit which consumes low power is proposed in this paper. The(More)
  • 1