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The logic of equality with uninterpreted functions has been proposed for verifying abstract hardware designs. The ability to perform fast satisfiability checking over this logic is imperative for such verification paradigms to be successful. We present symbolic methods for satisfiability checking for this logic. The first procedure is based on restricting… (More)
We define a notion of equivalence for designs containingblack boxes i.e., components whose functionality is notknown; these arise naturally in the course of hierarchicaldesign. Using this notion, we describe a sound andcomplete methodology for optimizing such designs.
We define a notion of equivalence for designs containing black boxes i.e., components whose functionality is not known: these arise naturally in the course of hierarchical design. Using this notion, we describe a sound and complete methodology for optimizing such designs.