Khaled Khalifa

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This paper presents a coverage driven constraint random based functional verification method based on the Universal Verification Methodology (UVM) using System Verilog for generic universal memory controller architecture. This universal memory controller is looking forward to improving the performance of the existing memory controllers through a complete(More)
In this paper, a novel common memory controller architecture is proposed. This common architecture includes the most major and important features for any manufacturer, these features can be enabled or disabled according to the manufacturer desire. This architecture can be utilized in any application according to desire of the manufacturer. Additionally,(More)
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