Kevin W. Rudd

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Recently, high-performance computer architecture has focused on dynamic scheduling techniques to issue and execute multiple operations concurrently. These designs are complex and have frequently shown disappointing performance. A complementary approach is the use of static scheduling techniques to exploit the same parallelism. In this paper we describe some(More)
Trends in high-performance computer architecture have led to the development o f i n-creased clock-rate and dynamic multiple-instruction issue processor designs. There have been problems combining both these techniques due to the pressure that the complex scheduling and issue logic puts on the cycle time. This problem has limited the performance of(More)
Deep-submicron technology allows billions of transistors on a single die, potentially running at gigahertz frequencies. According to Semiconductor Industry Association (SIA) projections, 1 the number of transistors per chip and the local clock frequencies for high-performance microprocessors will continue to grow exponentially in the near future, as Figure(More)
Trends in high-performance computer architecture have led to the development of increased clock-rate and dynamic multiple-instruction issue processor designs. There have been problems combining both these techniques due to the pressure that the complex scheduling and issue logic puts on the cycle time. This problem has limited the performance of(More)
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