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Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems
TLDR
We describe new multi-ported cache designs suitable for use in FPGA-based processor/parallel-accelerator systems, and evaluate their impact on application performance and area. Expand
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Visualization evaluation for cyber security: trends and future directions
TLDR
The Visualization for Cyber Security research community (VizSec) addresses longstanding challenges in cyber security by adapting and evaluating information visualization techniques with application to the cyber security domain. Expand
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Impact of FPGA architecture on resource sharing in high-level synthesis
TLDR
Resource sharing is a key area-reduction approach in high- level synthesis (HLS) in which a single hardware functional unit is used to implement multiple operations in the high-level circuit specification. Expand
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Finding the lost treasure: understanding reuse of used computing devices
TLDR
In this paper, we report our findings on the adoption practices of used personal digital assistants (PDAs) to inform reuse of outdated computing products. Expand
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Testing the technology: playing games with video conferencing
TLDR
Video connections can establish a media space in which games may be played, just as people play games while collocated. Expand
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FISH: Linux system calls for FPGA accelerators
TLDR
This, paper presents the FISH (FPGA-Initiated Software-Handled) framework which allows FPGA accelerators to make system calls to the Linux operating system in CPU-FPGA systems. Expand
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Advisory services for user composition tools
TLDR
We have developed an ontology based framework that evaluates compatibility between processing modules within an end user development framework, using MIT Lincoln Laboratory's Composable Analytics environment [1] as a test case. Expand
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