Kevin Harer

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We present <i>Ketchum,</i> a tool that was developed to improve the productivity of simulation-based functional verification by providing two capabilities: (1) <i>automatic test generation</i> and (2) <i>unreachability analysis.</i> Given a set of "interesting" signals in the design under test (<i>DUT</i>), automatic test generation creates input stimuli(More)
The architectural power intent of a design defines the intended global power states of a power-managed integrated circuit. Verification of the implementation of power management logic involves the task of checking whether only the intended power states are reached. Typically, the number of global power states reachable by the global power management(More)
We present a method for using a set of temporal properties (SVA, PSL, OVA, RTL monitors) as environment models for industrial-strength hybrid verification that combines formal methods with constrained random simulation. We demonstrate the effectiveness of the method on real-world designs.
With the growing complexity and gradually shrinking power requirements in the system-on-chip designs, sophisticated global power management policies (which orchestrate the switching between power states of multiple power domains) are commonplace. Recent research has paved some novel ways to verify the sophisticated on-chip architectural power management(More)
Livelock/deadlock is a well known and important problem in both hardware and software systems. In hardware verification , a livelock is a situation where the state of a design changes within only a smaller subset of the states reachable from the initial states of the design. Deadlock is a special case in which there is only one state in a livelock. However,(More)
We present a method that enables developing environment models or assumptions using properties in property languages like SVA, OVA and PSL, or using RTL monitors in design languages like Verilog and VHDL, for pseudo-random simulation, formal property verification and hybrid verification. Our method also includes automatic dead-end avoidance and enables(More)
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