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Journals and Conferences
Pattern matching in network applications is characterized by intensive computation. In conventional hardware accelerating methods, performance versus cost is a trade-off. In this paper, we proposed a new Hash-CAM hybrid architecture using state-of-the-art FPGA technology that is customized for a given pattern matching problem for DPI.
This paper discusses the need for new high-speed hardware architectures for future networks and in particular the need for high speed, high capacity shared buffer designs. An implementation of such a buffer using FPGA technology utilizing RLDRAM II is presented. The architecture that has been derived and implemented operated at 12.8 Gbps and is scalable up… (More)