Kerry Tedrow

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As flash memory cell size scales with lithography, the storage capacitance area scales resulting in the need to sense fewer electrons that are stored on a floating gate. A stepped-gate sensing scheme for NOR flash memories with multilevel storage are presented. Stepped-gate sensing motivation, scalability advantages and implementation are discussed.
The design of a flash-based reference voltage generator used to generate the drain bias reference voltage for flash sensing is described. The flash cell drain must maintain a stable voltage during read operation, irrespective of supply voltage within the chip, to avoid drain disturb condition. Since this reference voltage needs to supply the entire chip,(More)
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