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— This paper presents the first reported joint gate sizing and buffer insertion method for minimizing the delay of power constrained combinational logic networks that can incorporate a mixture of unbuffered and buffered gates (or mixture of CMOS and BiCMOS gates). In the method, buffered gates in a network are decided on by an iterative process that uses a(More)
This paper presents a method for optimizing BiCMOS logic networks that exploits the fact that such networks may use a mixture of both CMOS and BiCMOS gates. The method assumes a given network architecture and finds both the logic family and size for each gate so that total delay (power) is minimized subject to a power (delay) constraint. The method views a(More)
This paper presents the first reported discrete gate sizing method to jointly include library optimization capability. The method enables a designer to find the best set of sizes to include in a library and study the trade-off between the number of gate sizes in a library and circuit peTformance. Compared with continuous sizing, discrete sizing with library(More)
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