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- Ken-ichi Okada, Kento Yamaoka, Hidetoshi Onodera
- ASP-DAC
- 2003

This paper proposes a model to calculate statistical gate-delay variation caused by intra-chip and inter-chip variabilities. Our model consists of a statistical transistor model and a gate-delay model. We present a modeling and extracting method of transistor characteristics for the intra-chip variability and the inter-chip variability. In the modeling of… (More)

- Ken-ichi Okada, Kento Yamaoka, Hidetoshi Onodera
- ICCAD
- 2003

This paper proposes a model for calculating statistical gate-delayvariation caused by intra-chip and inter-chip variability. As thevariation of individual gate delays directly influences the circuit-delayvariation, it is important to characterize each gate-delay variationaccurately. Furthermore, as every transistor in a gate affectsthe transient… (More)

- Ken-ichi Okada, Kento Yamaoka, Hidetoshi Onodera
- ISCAS
- 2003

- An An, T. Yoshimasu, K. Yamaoka, S. Kurachi
- 2006 7th International Symposium on Antennas…
- 2006

This paper presents a design, simulation, implementation and measurement of a novel microstrip meander patch antenna for the application of sensor networks. The dimension of the microstrip chip antenna is 15 mm times 15 mm times 2 mm. The meander-type radiating patch is constructed on the upper layer of the 2 mm height substrate with 0.0 5 mm height… (More)

This paper proposes a model to calculate statistical gate-delay variation caused by intra-chip and inter-chip variabilities. The variation of each gate delay directly influences the circuitdelay variation, so it is important to characterize each gate-delay variation accurately. Every transistor in a gate affects transient characteristics of the gate, so it… (More)

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