Kento Yamaoka

Learn More
This paper proposes a model for calculating statistical gate-delayvariation caused by intra-chip and inter-chip variability. As thevariation of individual gate delays directly influences the circuit-delayvariation, it is important to characterize each gate-delay variationaccurately. Furthermore, as every transistor in a gate affectsthe transient(More)
This paper proposes a model to calculate statistical gate-delay variation caused by intra-chip and inter-chip variabilities. Our model consists of a statistical transistor model and a gate-delay model. We present a modeling and extracting method of transistor characteristics for the intra-chip variability and the inter-chip variability. In the modeling of(More)
  • 1