• Publications
  • Influence
Multi-center congestion estimation and minimization during placement
TLDR
We give a mathematical equation to predict the overflow within a region using a normal distribution approximation and propose the flexible expansion scheme in our multi-center congestion reduction (MC2R) algorithm. Expand
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Issues and approaches to coarse-grain reconfigurable architecture development
TLDR
We present three algorithms that solve this problem by balancing the hardware needs of the domain while considering performance and area requirements. Expand
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A snap-on placement tool
TLDR
We propose a new snap-on placement tool, which is based on multilevel hierarchical placement method, which produces very good results on all benchmarks and the best known result on the largest MCNC benchmark. Expand
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Armada: timing-driven pipeline-aware routing for FPGAs
TLDR
We present a new timing-driven pipeline-aware router that produces as much as 60% better critical path delay than previous efforts. Expand
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Simultaneous Retiming and Placement for Pipelined Netlists
TLDR
We introduce a new simulated annealing-based placement and retiming approach that provides the capability to aggressive apply retim on a wide range of netlists, for arbitrary architectures, while maintaining predictable results. Expand
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Enhancing timing-driven FPGA placement for pipelined netlists
TLDR
We discuss some of the inherent issues pipelined netlists pose to existing timing-driven placement approaches, and propose two algorithmic modifications to address them. Expand
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Architecture-adaptive range limit windowing for simulated annealing FPGA placement
TLDR
We propose an adaptive range limiter that controls the maximum distance by which any given block can be moved at different points of the annealing process. Expand
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RaPiD-AES: Developing an Encryption-Specific FPGA Architecture
TLDR
RaPiD-AES: Developing Encryption-Specific FPGA Architectures The Advanced Encryption Standard competition offered a compelling opportunity for designers to exploit the benefits of domain-specific FPGAs to produce a versatile, fast, and early-to-market encryption device. Expand
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Resource allocation for coarse-grain FPGA development
TLDR
The development of domain-specialized reconfigurable devices, and even the nature of domains themselves, has been largely unexplored. Expand
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Supporting high-performance pipelined computation in commodity-style fpgas
TLDR
This dissertation investigates the concerns that arise for both FPGA physical design tools and the architectures themselves.Although the popularity of Field Programmable Gate Arrays, or FPGAs, is a testament to their unique mixture of flexibility and ease of use, this adaptability can come at price. Expand
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