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We analyze relationships among local minima for the traveling salesman and graph bisection problems under standard neighborhood structures. Our work reveals surprising correlations that suggest a globally convex, or big valley" structure in these optimization cost surfaces. In conjunction with combinatorial results that sharpen previous analyses, our… (More)

40 is a near branch, an analogous argument again shows that Pin(b) is q's lower-right quadrant. Thus, q is the closest connection between p, Pin(a) and Pin(b). Except for redundancies and pruning of sub-optimal trees, BB-SORT-C searches over all possible ways to construct a Steiner tree sequentially, such that each sink is added by a closest connection to… (More)

We address the eecient construction of intercon-nection trees with near-optimal delays. We study the accuracy and delity of easily-computed delay models with respect to detailed simulation (e.g., SPICE-computed delays). We show that Elmore delay minimization is a high-delity interconnect objective for IC interconnect technologies, and propose a greedy low… (More)

We present two critical-sink routing tree (CSRT) constructions which exp!oit criticai-path information that becomes availab[e during timing-driven layout. Our CS-Steiner heuristics with " Giobai Slack Removal " modify traditional Stetner constructions and produce routing trees wtth szgntjicanthj lower critical-sink delays compared with existing… (More)

We provide a new theoretical framework for constructing Steiner routing trees with minimum Elmore delay. Earlier work 3, 13 has established Elmore delay as a high delity estimate of physical", i.e., SPICE-computed, signal delay. Previously, however, it was not known how to construct an Elmore delay-optimal Steiner tree. Our main theoretical result is a… (More)

Wire load models (WLMs) are generally perceived to be inaccurate and inadequate for good optimization. The traditional wisdom is that accuracy of WLMs will worsen as die sizes expand and feature sizes shrink, and as wire loads become less predictable and more dominant over pin loads. In many industry white papers and academic works, the weaknesses of WLMs… (More)

The simulated annealing SA algorithm 122 5 has been widely used to address intractable global optimizations in many elds, including training of arti-cial neural networks. Implementations of annealing universally use a monotone decreasing, o r c ool-ing", temperature s c h e dule which is motivated b y t h e algorithm's proof of optimality as well as… (More)

The simulated annealing SA algorithm 144 55 has been applied to every diicult optimization problem in VLSI CAD. Existing SA implementations use monotone decreasing, or cooling, t e m p erature s c h e d-ules motivated by the algorithm's proof of optimality as well as by an analogy with statistical thermodynamics. This paper gives strong evidence that… (More)

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