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We analyze relationships among local minima for the traveling salesman and graph bisection problems under standard neighborhood structures. Our work reveals surprising correlations that suggest a globally convex, or big valley" structure in these optimization cost surfaces. In conjunction with combinatorial results that sharpen previous analyses, our(More)
40 is a near branch, an analogous argument again shows that Pin(b) is q's lower-right quadrant. Thus, q is the closest connection between p, Pin(a) and Pin(b). Except for redundancies and pruning of sub-optimal trees, BB-SORT-C searches over all possible ways to construct a Steiner tree sequentially, such that each sink is added by a closest connection to(More)
We address the eecient construction of intercon-nection trees with near-optimal delays. We study the accuracy and delity of easily-computed delay models with respect to detailed simulation (e.g., SPICE-computed delays). We show that Elmore delay minimization is a high-delity interconnect objective for IC interconnect technologies, and propose a greedy low(More)
We present two critical-sink routing tree (CSRT) constructions which exp!oit criticai-path information that becomes availab[e during timing-driven layout. Our CS-Steiner heuristics with " Giobai Slack Removal " modify traditional Stetner constructions and produce routing trees wtth szgntjicanthj lower critical-sink delays compared with existing(More)
We provide a new theoretical framework for constructing Steiner routing trees with minimum Elmore delay. Earlier work 3, 13 has established Elmore delay as a high delity estimate of physical", i.e., SPICE-computed, signal delay. Previously, however, it was not known how to construct an Elmore delay-optimal Steiner tree. Our main theoretical result is a(More)
We address the eecient construction of inter-connection trees with near-optimal delay properties. We begin from rst principles, and study the accuracy and delity of easily-computed delay models (speciically, Elmore delay) with respect to detailed simulation of underlying physical phenomena (e.g., SPICE-computed delays). Our studies show that minimization of(More)
" The simulated annealing (SA) algorithm is widely used for heuristic global optimization due to its high-quality results and its ability, in theory, to yield optimal solutions with probability one. Standard SA implementations use monotone decreasing , or 'cooling' temperature schedules that are motivated by the algorithm's proof of optimality as well as by(More)