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The VPR toolset [6, 7] has been widely used to perform FPGA architecture and CAD research, but has not evolved over the past decade to include many architectural features now present in modern FPGAs. This paper describes a new version of the toolset that includes four significant features: first, it now supports a broad range of single-driver routing(More)
To facilitate the development of future FPGA architectures and CAD tools -- both embedded programmable fabrics and pure-play FPGAs -- there is a need for a large scale, publicly available software suite that can synthesize circuits into easily-described hypothetical FPGA architectures. These circuits should be captured at the HDL level, or higher, and pass(More)
Exploring architectures for large, modern FPGAs requires sophisticated software that can model and target hypothetical devices. Furthermore, research into new CAD algorithms often requires a complete and open source baseline CAD flow. This article describes recent advances in the open source Verilog-to-Routing (VTR) CAD flow that enable further research in(More)
In this work, we present Odin II, a framework for Verilog Hardware Description Language (HDL) synthesis that allows researchers to investigate approaches/improvements to different phases of HDL elaboration that have not been previously possible. Odin II’s output can be fed into traditional back-end flows for both FPGAs and ASICs so that these(More)
This paper discusses the hardware architecture used in the hw/sw co-design of a Java virtual machine. The paper briefly outlines the partitioning of instructions and support for the virtual machine. Discussion concerning the hardware architecture follows focusing on the special requirements that must be considered for the target environment. A comparison is(More)
The security of encryption algorithms depends heavily on the computational infeasibility of exhaustive key-space searches. We use the RC4 cipher, utilized primarily in the area of data communications, as a test case for determining the effectiveness of exhaustive key-searches implemented on FPGAs using a network on chip (NoC) design architecture.(More)
Hardened adder and carry logic is widely used in commercial FPGAs to improve the efficiency of arithmetic functions. There are many design choices and complexities associated with such hardening, including circuit design, FPGA architectural choices, and the CAD flow. There has been very little study, however, on these choices and hence we explore a number(More)
This paper discusses the initial results of research into the development of a hardware/software co-design of the Java virtual machine. The design considers a complete Java virtual machine with full functionality expected to run with the same capabilities as a fully software Java virtual machine. We address issues such as why a partial hardware(More)