Ken Papworth

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180 Kbit magnetoresistive random access memory (MRAM) designed for embedding in a 0.28 micron CMOS process has been developed. The memory cell is based on a 1-transistor 1-magnetic tunnel junction (1T1MTJ) bit cell. The architecture, write driver, and sense amplifier are described. The use of a test register to characterize and optimize the memory design is(More)
A 4 Mbit Magnetoresistive Random Access Memory (MRAM) with a new magnetic switching mode is described. The memory cell is based on a 1-Transistor 1-Magnetic Tunnel Junction (1T1MTJ) bit cell. The 4 Mbit MRAM circuit was designed in a five level metal, 0.18 /spl mu/m CMOS process with a bit cell size of 1.55 /spl mu/m/sup 2/. A new cell architecture, bit(More)
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