Learn More
To maintain high performance across a wide variety of applications, the first-generation CELL processor [1], fabricated in 90nm SOI CMOS, requires hundreds of gigabits of aggregate I/O bandwidth. In this paper, circuit design considerations and the clocking architecture of the 6.4Gb/s/link, 12B (7 TX + 5 RX) parallel I/O, Redwood Rambus ASIC cell (RRAC),(More)
Injection-locked clock multipliers (ILCMs) achieve superior phase noise compared to conventional PLLs [1, 2]. In its simplest form, an ILCM is an oscillator into which a train of narrow pulses is injected at reference frequency FREF as shown in Fig. 10.6.1. If the free-running frequency, FFR, of the oscillator is tuned close to NFREF (N=4, in Fig. 10.6.1),(More)
This paper describes the design of a novel CMOS 2 Gb/s asymmetric serial link. The serial link is designed for systems that use high speed chip-to-chip communications. In such designs, power dissipation is a common problem, particularly when multiple serial links are required on one chip. The power arises primarily from the phase adjustment circuitry used(More)
The IST-project VIRTUE is now in its last year of a 3-year project. The overall aim of this project is to realise a real-time 3D videoconferencing system creating a convincing impression of immersive telepresence. The system design is completed and we are now able to present the final 3D videoconference station including the whole architecture of the(More)