Kelly A. Ockunzzi

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A high-level test synthesis methodology based on BIST is proposed. This methodology targets the conditional if-then-else statements in a behavioral description because such statements can introduce testability problems in the resulting circuit. How well the operations in each branch of a conditional statement can be tested depends on the probability of(More)
h EMBEDDED MEMORIES OCCUPY most of the area on modern integrated circuits. Delay defect testing on the functional interface of a random access memory (RAM) can improve shipped product quality levels significantly. However, these tests are complicated because they require interaction at functional speeds between the memory and the surrounding functional(More)
The proposed BIST-based DFT method target testability problems caused by three constructs. The first construct is reconvergent fanout in a circuit behavior, which causes correlation. The second construct, control statements, also cause correlation and relational operations degrade observability. The third construct is random-pattern-resistant RTL modules,(More)
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