Keith A. Bowman

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A model describing the maximum clock frequency (FMAX) distribution of a microprocessor is derived and compared with wafer sort data for a recent 0.25m microprocessor. The model agrees closely with measured data in mean, variance, and shape. Results demonstrate that within-die fluctuations primarily impact the FMAX mean and die-to-die fluctuations determine(More)
A 65 nm resilient circuit test-chip is implemented with timing-error detection and recovery circuits to eliminate the clock frequency guardband from dynamic supply voltage and temperature variations as well as to exploit path-activation probabilities for maximizing throughput. Two error-detection sequential (EDS) circuits are introduced to preserve the(More)
A 45 nm microprocessor core integrates resilient error-detection and recovery circuits to mitigate the clock frequency guardbands for dynamic parameter variations to improve throughput and energy efficiency. The core supports two distinct error-detection designs, allowing a direct comparison of the relative trade-offs. The first design embeds(More)
Three circuit techniques for dynamic variation tolerance are presented: (i) Sensors with adaptive voltage and frequency circuits, (ii) Tunable replica circuits for timing-error prediction with error recovery, and (iii) Embedded error-detection sequential circuits with error recovery. These circuits mitigate the clock frequency guardbands for dynamic(More)
A new compact physics-based Alpha-Power Law MOSFET Model is introduced to enable projections of low power circuit performance for future generations of technology by linking the simple mathematical expressions of the original Alpha-Power Law Model with their physical origins. The new model, verified by HSPICE simulations and measured data, includes: 1) a(More)
A statistical performance simulator is developed to explore the impact of die-to-die (D2D) and within-die (WID) parameter variations on the distributions of maximum clock frequency (FMAX) and throughput for multi-core processors in a future 22nm technology.allThe simulator integrates a compact analytical throughput model, which captures the key dependencies(More)
Parameter variations have a great impact on maximum clock frequency. Designers set a processor’s clock frequency to allow for the worst-case critical-path delay plus a safety margin. This process, known as guardbanding, is necessary because delays are not constant: Variations in process, voltage, temperature, and input values (PVTI) all contribute to the(More)
Microprocessor clock frequency (FCLK) is traditionally determined based on maximum supply voltage (Vcc) droop and temperature specifications. Since typical usage patterns usually run at nominal Vcc and temperature, these infrequent dynamic variations severely limit FCLK. The concept of timing-error detection and correction in previous work [1,2] is extended(More)
Die-to-die and within-die variations impact the frequency and power of fabricated dies, affecting functionality, performance, and revenue. Variation-tolerant circuits and post-silicon tuning techniques are important for minimizing the impacts of these variations. This paper describes several circuit techniques that can be employed to ensure efficient(More)